A New Design of Full Adder based on XNOR-XOR Circuit
نویسندگان
چکیده
This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy efficient applications. It also shows nearly 82% improvement in threshold loss as compared to the existing 8T full adder. All simulations have been performed on 45nm standard model on Tanner EDA tool version 12.6. General Terms Power consumption and full adder.
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